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A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder
| Content Provider | Semantic Scholar |
|---|---|
| Author | Blanksby, Andrew J. Howland, Chris |
| Copyright Year | 2001 |
| Abstract | A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply. |
| Starting Page | 404 |
| Ending Page | 412 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/4.987093 |
| Volume Number | 37 |
| Alternate Webpage(s) | http://gladstone.systems.caltech.edu/~jeremy/other_papers/1GbpsLDPC.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/4.987093 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
