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An Efficient Test Compression Scheme based on LFSR Reseeding
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kim, Hong-Sik Kim, Hyunjin Ahn, Jin-Ho Kang, Sungho |
| Copyright Year | 2009 |
| Abstract | A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes. |
| Starting Page | 26 |
| Ending Page | 31 |
| Page Count | 6 |
| File Format | PDF HTM / HTML |
| Volume Number | 46 |
| Alternate Webpage(s) | http://soc.yonsei.ac.kr/Abstract/Korean_journal/pdf/An%20Efficient%20Test%20Compression%20Scheme%20based%20on%20LFSR%20Reseeding.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
