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A 65 nm 0.165 fJ/Bit/Search 256 $,times,$144 TCAM Macro Design for IPv6 Lookup Tables

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A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

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40 . 4 fJ / bit / mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45 nm SOI CMOS

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1.8 $Mbit/mm^{2}$ ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology

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A novel butterfly match-line scheme with don’t-care based hierarchical search-line for tcam.

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A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump

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