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Design and implementation of an FPGA-based processor for compressed images
| Content Provider | Semantic Scholar |
|---|---|
| Author | Balakrishnan, Venkataramanan S. Pottinger, Hardy J. Erçal, Fikret Agarwal, Mukesh Kumar |
| Copyright Year | 2000 |
| Abstract | This paper deals with the implementation of a systolic array architecture in hardware using FPGAs for processing compressed binary images without decompressing them. Specifically, run-length encoding (RLE) is used for compression. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed. |
| File Format | PDF HTM / HTML |
| DOI | 10.1117/12.403594 |
| Volume Number | 4118 |
| Alternate Webpage(s) | https://www.computer.org/csdl/proceedings/fpga/2000/2592/00/25920218.pdf |
| Journal | SPIE Optics + Photonics |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |