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Reversed-Trellis Tail-Biting Convolutional Code ( RT-TBCC ) Decoder Architecture Design for LTE
| Content Provider | Semantic Scholar |
|---|---|
| Author | Adiono, Trio Ramdani, Ahmad Zaky Putra, Rachmad Vidya Wicaksana |
| Copyright Year | 2018 |
| Abstract | Received Mar 8, 2017 Revised Nov 3, 2017 Accepted Nov 17, 2017 Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed. Keyword: |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.iaescore.com/journals/index.php/IJECE/article/download/10114/8106 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
