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Energy Efficient Mapping in 3 D Mesh Communication Architecture for NoC By Pranav Wadhwani ,
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wadhwani, Pranav Choudhary, Naveen Singh, Dharm Prakash |
| Copyright Year | 2013 |
| Abstract | By the end of this decade we will be entering into the era of thousand cores SoCs. 3D integration technologies have opened the door of new opportunities for NoC architecture design in SoCs providing higher efficiency compared to 2D integration by appropriately adjusting the increased path lengths of 2D NoC. The application to core mapping on NoC architecture can significantly affect the amount of system's dynamic communication energy consumption. The considerable amount of energy savings can be achieved by appropriately optimizing the application to core mapping in NoC architecture. This paper presents a Branch-and-Bound heuristic for smart application to core mapping in 3D Mesh NoC architecture. Experimental results show that proposed heuristic saves about 42%-55% and 19%-28% of dynamic communication energy consumption in comparison to random mapping in 3D NoC communication architecture and the energy aware-mapping in 2D NoC architecture of same size, respectively. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://globaljournals.org/GJCST_Volume13/1-Energy-Efficient-Mapping.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
