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A Design Technique for High-Performance Self-Checking Combinational Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Dubrova, Elena |
| Copyright Year | 2001 |
| Abstract | In this paper, we present a new technique for design of the functional part of a self-checking combinational logic circuit, targeting high-performance applications. Our implementation is three-level AND-OR-AND logic, with the first two levels realized by PLAs and the third level realized by two-input AND gates. The outputs of the circuit are encoded in Berger code. Since such a design has inverters only on primary inputs, the polarity of the error produces on the output is the same as the polarity of the fault which caused this error. Therefore, the majority of realistic single faults and of the multiple stuck-at faults result in an unidirectional error on the output which are detected by Berger code. Experimental results show that, on average, an AND-OR-AND implementation with outputs encoded in Berger code is smaller (19%) than the non-encoded twolevel PLA implementation of the same function. |
| Starting Page | 11 |
| Ending Page | 15 |
| Page Count | 5 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://web.it.kth.se/~dubrova/PAPERS/TEST01.pdf |
| Alternate Webpage(s) | http://www.ele.kth.se/~elena/PAPERS/TEST01.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
