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Realisation of Vedic Multiplier Using Urdhva Tiryakbhayam Sutra
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lakshmi, N. Bhagya Lakshmi, Bommidi Vijaya |
| Copyright Year | 2014 |
| Abstract | Multiplication is the one of the basic arithmetic operations and it requires and more processing time and power than other arithmetic operations like addition and subtraction. So, multiplier design is always a challenging task, however many designs are proposed, the user needs demands much more optimized ones. Vedic mathematics provides some algorithms that evaluate fast results, both in mental calculations or hardware design. Power dissipation is continuously reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper the modified design increase the performance by maintain the design functionality without any degradation. The Total Reversible Logic Implementation Cost (TRLIC) evaluate the proposed design. This multiplier has application over designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijves.com/wp-content/uploads/2012/07/IJVES-Y14-11491.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
