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A 622 Mbps burst mode CDR with jitter reduction capability
| Content Provider | Semantic Scholar |
|---|---|
| Author | Han, Pyung-Su Lee, Cheon-Oh Choi, Woo-Young |
| Copyright Year | 2003 |
| Abstract | This paper describes a novel burst-mode CDR(Clock and Data Recovery) circuit can be used in 622Mbps burst mode applications. The designed circuit is basically a PLL(Phase Locked Loop) has 2 PD(Phase Detector)s each for reference clock and NRZ type data, altered by external control signal. This CDR was fabricated in 1-poly 5-metal 0.25 μ m CMOS technology. Jitter generation, burst/continuous mode data receptions were tested and experimental results are presented. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://tera.yonsei.ac.kr/publication/pdf/2003_pshan_SDC.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
