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Design of Parallel Decimal Multiplier using Limited Range of Signed-Digit Number Encoding
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hwang, In-Guk Kim, Kanghee Yoon, Wan-Oh Choi, Sang-Bang |
| Copyright Year | 2013 |
| Abstract | In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion. |
| Starting Page | 50 |
| Ending Page | 58 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.5573/ieek.2013.50.3.050 |
| Volume Number | 50 |
| Alternate Webpage(s) | http://ocean.kisti.re.kr/downfile/volume/ieek/DHJJQ3/2013/v50n3/DHJJQ3_2013_v50n3_50.pdf |
| Alternate Webpage(s) | https://doi.org/10.5573/ieek.2013.50.3.050 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
