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Bit-sliced design of a graph reduction processor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Vireday, Richard Pierre |
| Copyright Year | 1986 |
| Abstract | Bit-Slice Design of a Graph Reduction Processor Richard P. Vireday Oregon Graduate Center, 1986 Supervising Professor: Richard B. Kieburtz The G-Machine is an abstract architecture t h a t t o supports languages with graph computing models by utilizing software technologies t o provide efficient graph manipulation on sequential machines. Graph computing models are different than those for s tandard imperative languages, and support for graph manipulation is generally lacking on machines designed for s tandard imperative languages. The architecture is stack-based and manipulates graphs via pointers, a pointer stack, and tagged memories. The tags and pointer stack also help provide a n effective method of performing "lazy" evaluation, a computing technique t h a t allows for execution of many complex algorithms. In this thesis, the abstract G-Machine Architecture has been redefined t o provide a ceprocessor implementation. The heart of the G-Machine ceprocessor is the Program Execution Unit (PCU), a conceptually simple processor which can be implemented in a variety of ways. A design for the PCU is shown t h a t is simple t o build and program, utilizes existing technology, and provides complete support for the abstract G-Machine |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://digitalcommons.ohsu.edu/cgi/viewcontent.cgi?article=1223&context=etd&httpsredir=1&referer= |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
