NDLI: Digital Signal Processor based Hardware Implementation of Current Error Space Phasor based Hysteresis Controller for Two-level Shunt Active Power Filter

Please wait, while we are loading the content...

Digital Signal Processor based Hardware Implementation of Current Error Space Phasor based Hysteresis Controller for Two-level Shunt Active Power Filter

Content Provider	Semantic Scholar
Copyright Year	2014
Abstract	A laboratory scale prototype model of the proposed controller based SAPF has been developed using DSP TMS320LF2407A. IGBT based two-level converter is fabricated and used as SAPF. Three-phase diode bridge rectifier with capacitor filter and resistive load is used as non-linear load (harmonic current generating load). Reference compensating currents are generated by Fryze current computation technique using DSP. As the proposed current controller based SAPF is versatile in nature, it can work for any reference compensating current generation schemes as depicted from results of Chapter-5 and Chapter-6. The current error space phasor based hysteresis controller for two-level SAPF is experimentally implemented for sector change detection without using outer hysteresis band as well as with outer hysteresis band. The proposed controller based SAPF, without using outer hysteresis band is experimentally implemented with sector change detection by instantaneous values of three-phase voltages at the point of common coupling. The another logic (discussed in Chapter4) for identifying necessary sector changeovers (without using outer hysteresis band), sector change detection by instantaneous values of voltages at the point of common coupling, is not implemented practically as it suffers drawbacks of not being able to detect the frequency change between two consecutive zero crossing detections, which is quite possible in practical conditions. Reference compensating current calculation scheme along with proposed current controller logic is implemented in DSP. Entire
File Format	PDF HTM / HTML
Alternate Webpage(s)	http://shodhganga.inflibnet.ac.in:8080/jspui/bitstream/10603/28248/17/17_chapter_7.pdf
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in