Leveraging Systemc and Ocp to Improve the Verification of Fpga-based Software Defined Radios

Content Provider	Semantic Scholar
Author	Noseworthy, Joshua
Copyright Year	2007
Abstract	The design complexity of the modern day Software Defined Radio (SDR) is increasing as system designers continue to explore ways to successfully integrate Field Programmable Gate Arrays (FPGAs) into SDR-based systems. One of the many challenges associated with the integration of FPGAs into SDR-based systems is verification at both the component and system levels. Unlike software-based components which can rely on common interface standards such as those set forth by the Software Communication Architecture (SCA), FPGAbased components have no common standard upon which to draw. This makes it extremely difficult to leverage verification Intellectual Property (IP) assets across multiple FPGA-based components since each component could potentially have a unique interface. The result is a time-consuming process of customizing verification IP to suite the needs of a particular FPGA component interface. Another challenge of introducing FPGAs into SDRbased systems is verification at the system or application level. Typical systems are heterogeneous, containing a mix of FPGAs and other devices operating at varying levels of abstraction. This degree of heterogeneity makes the provision of a single verification environment, in which both hardware and software elements can be verified, difficult. These challenges can be alleviated through the introduction of modeling languages, such as SystemC, that are capable of supporting varying levels of modeling abstraction and standardized interface techniques for FPGA components, such as those described by the Open Core Protocol (OCP). SystemC provides a C++ based standard for the specification of both hardware and software systems at varying levels of abstraction. SystemC is capable of modeling at both the abstract transaction level and the Register Transfer Level (RTL), as well as at levels in between. Many commercially available hardware description language (HDL) simulators offer mixed-language environments where SystemC models can interact with both VHDL and Verilog models. This creates a powerful verification environment that enables designers to fully test and verify their synthesizable RTL together with C/C++ based structures. In addition, this type of environment allows for the co-verification of the application’s FPGA and software-based components prior to the application’s actual deployment.
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Language	English
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Content Type	Text
Resource Type	Article