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Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers
| Content Provider | Semantic Scholar |
|---|---|
| Author | Liu, Yu-Chia Tsai, Ming-Han Tang, Tsung-Lin Fang, Weileun |
| Copyright Year | 2011 |
| Abstract | This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel. |
| Starting Page | 105005 |
| Ending Page | 105005 |
| Page Count | 1 |
| File Format | PDF HTM / HTML |
| DOI | 10.1088/0960-1317/21/10/105005 |
| Volume Number | 21 |
| Alternate Webpage(s) | http://mdl.pme.nthu.edu.tw/nthu_pme_lab_eng/papers/115.pdf |
| Alternate Webpage(s) | https://doi.org/10.1088/0960-1317%2F21%2F10%2F105005 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
