NDLI: Method for Failure Analysis of Megachips Using Scan Techniques Field of the Invention

Content Provider	Semantic Scholar
Copyright Year	2017
Abstract	Testing of a semiconductor integrated circuit is conducted by determining all paths leading to a failed location on a chip. Potentially faulty locations are then determined by finding faults which occurred at the same time the failing vector was scanned, and the intersection of the paths and the faulty locations form a smaller set of potentially faulty locations on the IC. Further testing of the nodes which are in this smaller set is performed until a single location or small portion of a chip may be visually inspected with little effort.
File Format	PDF HTM / HTML
Alternate Webpage(s)	https://patentimages.storage.googleapis.com/62/88/e6/85ce1f05437d80/US5550841.pdf
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

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