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1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuit Using Gated-Oscillators
| Content Provider | Semantic Scholar |
|---|---|
| Author | Han, Pyung-Su Choi, Woo Young |
| Copyright Year | 2005 |
| Abstract | A burst-mode clock recovery circuit with a novel dual-mode structure is presented. It utilizes two gated-oscillators to align recovered clock edges to data. It can operate in double data-rate mode in which both rising and falling edges of recovered clock are used. To enable this, gated-oscillator reset-phase control scheme is introduced to switch the starting phase of gated-oscillator dynamically between 0° and 180° according to current clock phase. A prototype chip was designed with 0.18μm CMOS technology, whose 1.25/2.5-Gb/s dual-mode clock recovery operation is successfully verified by SPICE simulation. |
| Starting Page | 251 |
| Ending Page | 255 |
| Page Count | 5 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://tera.yonsei.ac.kr/publication/pdf/conf_2005_pshan_isocc.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
