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A 9.95–11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kenney, J. G. Dalton, Declan Evans, Erica Eskiyerli, M. H. Hilton, Benjamin Hitchcox, D. Kwok, T. Mulcahy, David McQuilkin, C. Reddy, Vimala Selvanayagam, S. Shepherd, Paul Titus, W. S. DeVito, L. M. |
| Copyright Year | 2006 |
| Abstract | A 9.95-11.3-Gb/s transceiver in 0.13-mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12'' of FR4 is equalized resulting in system JGEN under 4 mUIRMS and 35 mUI PP. Power consumption is 800 mW |
| Starting Page | 2901 |
| Ending Page | 2910 |
| Page Count | 10 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/JSSC.2006.884344 |
| Volume Number | 41 |
| Alternate Webpage(s) | http://www.revsemi.com/files/documents/XFP_JSSC.pdf |
| Journal | IEEE Journal of Solid-State Circuits |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
