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Efficient method of Low Power Variable Latency Multiplier with AH Logic
| Content Provider | Semantic Scholar |
|---|---|
| Author | Monika, G. Rao, Kethireddipalli S. |
| Copyright Year | 2016 |
| Abstract | High speed and low Power consumption is one of the most important design objectives in integrated circuits. As multipliers are the most widely used components in such circuits, the multipliers must be design efficiently. This paper proposes the simple and efficient approach to reduce the maximum power consumption and delay. Based on the idea of razor flip flop and adaptive hold logic the timing violations are reduced. In the fixed latency usage of clock cycles is increased. The re execution of clock cycles is reduced by using variable latency. The result analysis shows that the reliable multiplier has better performance in power consumption and delay than contemporary architectures. |
| Starting Page | 421 |
| Ending Page | 425 |
| Page Count | 5 |
| File Format | PDF HTM / HTML |
| Volume Number | 3 |
| Alternate Webpage(s) | http://www.ijsr.net/archive/v4i2/SUB151615.pdf |
| Alternate Webpage(s) | https://www.ijsr.net/archive/v4i2/SUB151615.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
