Loading...
Please wait, while we are loading the content...
Design of a Low Latency Asynchronous Adder Using Early Completion Detection
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lai, Kok Keong Chung, Edwin Chin Yau Lu, Shih-Lien Quigley, Steven F. |
| Copyright Year | 2014 |
| Abstract | A new method for designing completion detection for asynchronous adders is introduced. The new completion detection is based on the property of a carrymerge tree for parallel-prefix adders where a generate bit at one level will have the same value as that in the previous level if there is no carry into the sequence of bits. This method has the advantages of a bundled data approach, allowing the use of single-rail completion detection design methodology, yet it allows the detection of early completion with very minimal gate count overhead. An alternative to "speculative completion," this method has approximately 10% improvement in performance at the costs of a 4% increase in area and a negligible increase in power consumption for Hybrid Skalansky Carry-Select and self-timed Kogge-Stone parallel prefix adders. |
| Starting Page | 755 |
| Ending Page | 772 |
| Page Count | 18 |
| File Format | PDF HTM / HTML |
| Volume Number | 9 |
| Alternate Webpage(s) | http://jestec.taylors.edu.my/Vol%209%20Issue%206%20December%2014/Volume%20(9)%20Issue%20(6)%20755-767.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
