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v 2 c – A Verilog to C Translator ?
| Content Provider | Semantic Scholar |
|---|---|
| Author | Mukherjee, Rajdeep Tautschnig, Michael Kroening, Daniel |
| Copyright Year | 2016 |
| Abstract | We present v2c, a tool for translating Verilog to C. The tool accepts synthesizable Verilog as input and generates a word-level C program as an output, which we call the software netlist. The generated program is cycle-accurate and bit precise. The translation is based on the synthesis semantics of Verilog. There are several use cases for v2c, ranging from hardware property verification, coverification to simulation and equivalence checking. This paper gives details of the translation and demonstrates the utility of the tool. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.cs.ox.ac.uk/people/rajdeep.mukherjee/tacas-appendix.pdf |
| Alternate Webpage(s) | http://www.kroening.com/papers/tacas2016-2.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
