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Crosstalk Delay Analysis in Very Deep Sub-micron Vlsi Circuits Crosstalk Delay Analysis in Very Deep Sub-micron Vlsi Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Thornton, Mitch Nair, Sukumaran Prasad, Satyendra Ravi Datla, Raju |
| Copyright Year | 2004 |
| Abstract | iii ACKNOWLEDGEMENTS I want to take the opportunity to thank all the people who supported this project. In particular, I owe a great deal of gratitude to my advisor, Professor Mitch Thornton, who encouraged me all throughout this project and helped me organize the work. My special thanks to Professor Sukumaran Nair and Professor John Provence for readily agreeing to be on the thesis committee. I also thank them for providing very useful suggestions during the project work. I here by thank all the friends and staff in CSE, EE and Research Departments for helping me during the project and for providing help during the thesis writing. I also thank my mother for her unwavering support during the many long days that went into this endeavor. I am also grateful to all of my other family members and wellwishers whose love and care for me always inspired me. Integrated Circuit design has seen revolutionary progress in the past quarter century. Explosive growth of semiconductor applications has occurred as a result of several technological breakthroughs. The IC design community today is embracing sub-100nm wafer design technologies, known as very deep sub-micron (VDSM) technologies, to take advantage of the superior integration possibilities. At these technologies, many phenomena affect gate and wire delays. Capacitive coupling between neighboring wires is one such phenomenon that is having significant effect on design's timing and functionality goals. The accurate estimation of these effects is a 'must have' requirement for any design that is manufactured using the VDSM technologies. This thesis summarizes the study conducted to identify the root causes of the crosstalk occurrence because of capacitive coupling. A case study was conducted on a complex VLSI design to check on the possible effects of the crosstalk on the design's timing and functionality goals. An efficient methodology to analyze and decimate crosstalk problem was developed and its effectiveness was compared with other available approaches. Some innovative methods are proposed to address the crosstalk problem well ahead in the design flow.. 1 Chapter 1 THESIS OVERVIEW This report presents the work conducted as part of my master's thesis. The topic chosen for this thesis is one of the current issues the VLSI (very large scale integration) design community is facing today: Signal Integrity. One of the major contributors of signal integrity problem is the crosstalk between the wires on an Integrated Circuit. This thesis reports the details of the … |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://engr.smu.edu/~mitch/ftp_dir/pubs/datla_thesis.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
