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A Hardware Accelerator Design Process for Speech Recognition Application
| Content Provider | Semantic Scholar |
|---|---|
| Author | Buitrago, Bonilla Aguirre, Johnny A. Benavides, Andrés Mauricio Hurtado Rivera, Marcela |
| Copyright Year | 2013 |
| Abstract | This paper shows a methodology to improve time response in a sub-stage inside a complete speech recognition system, and shows how to apply such methodology to other stages inside the same process. This methodology involves hardware and software cooperative work based on soft-core design using MicroBlaze processors and reconfigurable hardware in Xilinx Spartan 3E FPGA. Design process, proposed methodology, software and hardware components, and the migration approach are described and analyzed along with the process results. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://worldcomp-proceedings.com/proc/p2013/ESA2562.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
