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High-Resolution Multi-Bit Incremental Converter with 1 . 5-μ V Residual Offset and 94-dB SFDR
| Content Provider | Semantic Scholar |
|---|---|
| Author | Agnes, Andrea Bonizzoni, Edoardo Galdi, Ivano Maloberti, Franco |
| Copyright Year | 2010 |
| Abstract | This paper presents an incremental converter, based on a second order scheme, able to achieve 19 bit of resolution with 512 clock periods. The design avoids an initial error by an optimal reset of the two integrators, uses a 3-bit quantizer that enhances the resolution, and cancels the offset with a novel technique based on single or double chopping. The circuit, fabricated in a mixed 0.18-0.6 μm CMOS technology, obtains 1.5-μV residual offset with 2VPP fully differential range. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ims.unipv.it/~franco/ConferenceProc/309.pdf |
| Alternate Webpage(s) | http://sms.unipv.it/~franco/ConferenceProc/309.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
