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A 1.25-GHz 0.35-/spl mu/m monolithic CMOS PLL based on a multiphase ring oscillator
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sun, Lizhong Kwasniewski, Tadeusz A. |
| Copyright Year | 2001 |
| Abstract | A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast s뿮dback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a s뿮dback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-/spl mu/m CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply. |
| Starting Page | 910 |
| Ending Page | 916 |
| Page Count | 7 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/4.924853 |
| Volume Number | 36 |
| Alternate Webpage(s) | http://www.doe.carleton.ca/~tak/publications/journal/00924853.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
