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An instruction fetch and translation unit for the G- processor of the G-machine
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 1988 |
| Abstract | An Instruction Fetch and Translation Unit for the G-processor of the G-machine Shyue Ling Kuo Oregon Graduate Center, 1987 Supervising Professor: Richard B. Kieburtz The G-machine project is to study architecture support for the evaluat.ion of functional language by programmed graph reduction. One area of interest is to build a high performance instruction fetch unit. In this thesis, the design, implementation and performance of an instruction fetch and translation unit (IFTU) for the G-machine is described. The IFTU is a microprogrammed sequential processing unit, it supports high level abstraction (G-code instruction set) and produces simple instructions (horizontal like microcode) for fast execution. Hardware support is provided for all control transfer G-code instructions to enable early instruction prefetching. Other IFTU features are : pipelined design, two way instruction prefetching, early decoding, delayed jump implementation and proper buffer placement. A microsimulator of the IFTU has been built and integrated into the G-processor microsimulator. The IFTU's performance has been studied by running benchmark programs on the G-processor microsimulator. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://digitalcommons.ohsu.edu/cgi/viewcontent.cgi?article=1252&context=etd&httpsredir=1&referer= |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
