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OpenCL-Based High-Performance 3 D Stencil Computation on FPGAs Extended Abstract
| Content Provider | Semantic Scholar |
|---|---|
| Author | Zohouri, Hamid Reza Podobas, Artur Maruyama, Naoya Matsuoka, S. |
| Copyright Year | 2017 |
| Abstract | In recent years, power usage and efficiency has become a major concern in high-performance computing (HPC). FPGAs, due to their low power consumption and architectural flexibility, are slowly finding their way in HPC. With the recent advancements in High-Level Synthesis (HLS), especially availability of OpenCL from FPGA manufacturers, these devices can now be considered as a viable alternative for common HPC accelerators like GPUs. Stencils are one of the important computation patterns in HPC, used in solving PDEs and many different types of scientific simulations. In this work we show that for 3D stencil computation, due to architectural advantage of FPGAs, apart from superior power efficiency, we can also achieve competitive performance compared to a highly-optimized implementation on high-end GPUs. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://sc17.supercomputing.org/SC17%20Archive/tech_poster/poster_files/post114s2-file3.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Notes |
