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Scalable and Reconfigurable Digital Front-End for SDR Wideband Channelizer
| Content Provider | Semantic Scholar |
|---|---|
| Author | Savir, Gil |
| Copyright Year | 2006 |
| Abstract | Faculty of Electrical Engineering, Mathematics and Computer Science CE-MS-2006-16 I n recent years, RF receiver designers concentrated on replacing analog components with digital ones, striving towards the ideal Software Defined Radio (SDR) where all signal processing is done in software. Such an ideal SDR platform may form an exceptionally flexible and reprogrammable receiver that can cope with many different standards, e.g., IS-95, GSM, UMTS, and especially the various military standards. A wideband receiver has to simultaneously deal with hundreds to few thousands channels, which lay in the same spectrum interval. One of the most computation intensive tasks in such receiver is channelization [1]. A wideband channelizer decomposes its RF input signal into separate outputs, each containing the signal of single channel. In the past, practical limitations such as state-of-the-art digitizers' speed and computing capacity prevented the realization of a wideband SDR receiver. At present, these implications can be overcome using digital front-end architectures, comprising reconfigurable and scalable components (e.g., FPGA, FFTprocessors) allowing flexible and efficient implementation. The goal of the presented research is to study, design, and implement a flexible and reconfigurable wideband channelizer architecture that can be implemented on state-of-the-art FPGAs. In this dissertation, we present our work where we first choose a suitable algorithm for wideband channelization. The chosen algorithm employs an analysis DFT filterbank [2] that requires fewer hardware resources compared to other channelization algorithms. Subsequently, we simulate this algorithm for a broad range of practical parameters in order to determine hardware design requirements and performance trade-offs. Using the parameters survey, a test-case is devised and implemented on FPGA using our implementation architecture. Subsequently, the implementation results are compared to the simulation results in order to validate the parameter ranges survey. Scalable and Reconfigurable Digital Front-End for SDR Wideband Channelizer |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ce.et.tudelft.nl/publicationfiles/1206_716_Gil_Savir-MSc_thesis.pdf |
| Alternate Webpage(s) | https://omidi.iut.ac.ir/SDR/2007/Presentations/shimakheradmand/Channelization%20Techniques/1206_716_Gil_Savir-MSc_thesis.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Thesis |
