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Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lin, Chun-Yu Fan, Mei-Lian |
| Copyright Year | 2014 |
| Abstract | The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup. |
| Starting Page | 775 |
| Ending Page | 777 |
| Page Count | 3 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/TDMR.2014.2311130 |
| Volume Number | 14 |
| Alternate Webpage(s) | http://web.ntnu.edu.tw/~cy.lin/Referred_Journal_Papers/2014%20TDMR_Optimization%20on%20layout%20style%20of%20diode%20stackup%20for%20on-chip%20ESD%20protection.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/TDMR.2014.2311130 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
