Loading...
Please wait, while we are loading the content...
Similar Documents
A Multipurpose Design Framework for Hardware-Software Cosimulation of System-on-Chip
| Content Provider | Semantic Scholar |
|---|---|
| Author | Joo, Young-Pyo Yun, Dukyoung Kim, Sungchan Ha, Soonhoi |
| Copyright Year | 2008 |
| Abstract | As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully. |
| Starting Page | 485 |
| Ending Page | 496 |
| Page Count | 12 |
| File Format | PDF HTM / HTML |
| Volume Number | 35 |
| Alternate Webpage(s) | http://s-space.snu.ac.kr/bitstream/10371/7979/1/dbpia1068403.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
