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A Pseudo-12 bits Successive Approximation ADC for CMOS Image Sensors (Utilisation d'un ADC SAR pseudo-12 bits dans un capteur d'image CMOS)
| Content Provider | Semantic Scholar |
|---|---|
| Author | Marktani, Malika Alami Vivien, Stephane Elhachimi, Mhamed Ahaitouf, Ali Ahaitouf, Abdelaziz |
| Copyright Year | 2010 |
| Abstract | This paper illustrates the design of an original an alogue-to-digital conversion architecture in a CMOS Image Sensor using a pseudo-12 bits Successive Approximation (SA) ADC. The proposed architecture works like a conventional SA-ADC, and presents a special feature: as a CMOS Image Sensor is an application where the noise depends on the signal amplitude, the resoluti on of the system depends on the value of the signal s to be converted. The effective resolution of the converte r is 9 bits, but the global resolution is 12 bits. The signal to be converted is compared with a threshold corresponding to 1/8 of the full scale. If the signal is gre ater than the threshold, the conversion results over 9 bits a re used as the nine (9) LSBs of a twelve (12) bits word, the 3 remaining MSBs are set to 000, and thus the achie ved resolution of the converter is 12bits. Otherwis e if the signal is smaller than the threshold, the conversio n results over 9 bits is used as the 9 MSBs of a 12 bits word, the 3 remaining LSBs are obtained randomly, and in this case, thus the resolution of the convert er is pseudo-12bits. The converter uses fully differentia l charge redistribution DAC, a regenerative track a nd latch comparator and successive approximation registers. The transition between 9 bits and 12 bits is provid ed by an output stage responsible of adding 3 LSBs or 3 M SBs to the conversion results over 9 bits depending on the comparison value. At the end of the conversion, this SA-ADC gives the equivalent of a ramp startin g with code 0 and finishing with code 4095, which rep resents the 4096 codes of a 12 bit converter. The proposed design presents the benefit of increasing the number of bits of an ADC without excessively increasing its complexity or its processing time. The converter is designed in CMOS 65nm technology, and will be implemented in a 5Megapixel sensor, at a sa mpling rate of 8.33MS/s. The measurements show good linearity and verify the concept of the new archite cture. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.jmaterenvironsci.com/Document/vol1_Supp/3-JMES-S33-2010.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
