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Modeling and sizing for minimum energy operation in subthreshold circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Calhoun, B. B. Wang, A. Chandrakasan, A. P. |
| Copyright Year | 2005 |
| Abstract | This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V/sub DD/ and V/sub T/ to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-/spl mu/m test chip is used to compare normal sizing and sizing to minimize operational V/sub DD/ and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits. |
| Starting Page | 1778 |
| Ending Page | 1786 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/JSSC.2005.852162 |
| Volume Number | 40 |
| Alternate Webpage(s) | http://www-mtl.mit.edu/researchgroups/icsystems/pubs/journals/2005_calhoun_jssc_sept.pdf |
| Alternate Webpage(s) | http://rlpvlsi.ece.virginia.edu/sites/default/files/Calhoun_JSSC05.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/JSSC.2005.852162 |
| Journal | IEEE Journal of Solid-State Circuits |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
