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A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hasan, Ahmad Fariz Murad, Sohiful Anuar Zainol Bakar, Faizah Abu |
| Copyright Year | 2019 |
| Abstract | A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications. |
| Starting Page | 1859 |
| Ending Page | 1866 |
| Page Count | 8 |
| File Format | PDF HTM / HTML |
| DOI | 10.12928/telkomnika.v17i4.12761 |
| Volume Number | 17 |
| Alternate Webpage(s) | http://journal.uad.ac.id/index.php/TELKOMNIKA/article/download/12761/pdf_1130 |
| Alternate Webpage(s) | https://doi.org/10.12928/telkomnika.v17i4.12761 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |