NDLI: Impacts of gate recess and passivation on AlGaN/GaN high electron mobility transistors

Please wait, while we are loading the content...

Impacts of gate recess and passivation on AlGaN/GaN high electron mobility transistors

Content Provider	Semantic Scholar
Author	Chan, Chih-Yuan Lee, Ting-Chi Hsu, Shawn S. H. Chen, Leaf Lin, Yu-Syuan
Copyright Year	2007
Abstract	In this study, the impacts of gate recess and passivation on AlGaN/GaN high electron mobility transistors (HEMTs) were investigated. The trap-related characteristics were studied in detail by several different measurements including dc current– voltage, current collapse, gate lag, and flicker noise characterizations. With a Cl2/Ar-recessed gate, drain current collapse factors (� Imax )o f� 37:5 and � 6:9% were observed before and after SiN passivation. The gate lag measurements showed that the lagging phenomena almost disappear with SiN passivation for both Cl2- and Cl2/Ar-recessed devices. However, the flicker noise measurements revealed distinct noise levels of devices with different processes even after passivation. As the gate voltage (VG) changed from 2 to � 4 V, the devices recessed by Cl2 exhibited lower drain noise current densities (SID=ID 2 ranging from 2:8 � 10 � 14 to 1:7 � 10 � 12 Hz � 1 at 1 kHz) than those etched by Cl2/Ar mixture gas (SID=ID 2 ranging from 6:3 � 10 � 14 to 6:0 � 10 � 12 Hz � 1 at 1 kHz), whereas the devices without the recess process showed the lowest noise levels (SID=ID 2 ranging from 2:8 � 10 � 15 to 1:3 � 10 � 13 Hz � 1 at 1 kHz). It was found that SID=ID 2 increased monotonically when VG
Starting Page	478
Ending Page	484
Page Count	7
File Format	PDF HTM / HTML
DOI	10.1143/JJAP.46.478
Volume Number	46
Alternate Webpage(s)	http://www.ee.nthu.edu.tw/shhsu/journal%20papers/Gate%20recess%20GaN%20Hemt_JJAP.pdf
Alternate Webpage(s)	https://doi.org/10.1143/JJAP.46.478
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in