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Low Power Driven High-Level Synthesis for Dedicated Architectures
| Content Provider | Semantic Scholar |
|---|---|
| Author | Rettberg, Achim |
| Copyright Year | 2007 |
| Abstract | This paper describes a method to integrate low power scheduling and partitioning into high-level synthesis. The high-level synthesis approach is especially developed for a bitserial architecture. We addressed a specific analysis technique within the scheduling task of high-level synthesis. The analysis technique allows the determination of dedicated turn-on and turn-off mechanism by design partitioning. Therefore, the optimisation of power consumption is simultaneously improved with the design delay for the target architecture. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.uni-paderborn.de/fachbereich/AG/rammig/www/members/berndk/PS/nasa03-lowpower.pdf |
| Alternate Webpage(s) | http://wwwcs.upb.de/fachbereich/AG/rammig/www/members/berndk/PS/nasa03-lowpower.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |