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Synthesizing Full-Systolic Arrays For Matrix Product On Xilinx ' s XC 4000 ( E , EX ) FPGAs
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hartenstein, Reiner W. Herz, Michael Hoffmann, Thomas Nageldinger, Ulrich Oudjida, Abdelkrim Kamel Titri, S. Hamarlain, Mustapha |
| Copyright Year | 2004 |
| Abstract | We introduce a concept for reconfigurable hardware platforms along with an according CAD framework. The framework is not restricted to a specific architecture, but is capable of generating mappings for a number of members of the coarse grain reconfigurable KressArray architecture family, and similar platforms. Based on the multi-architecture CAD framework, a design-exploration environment has been set up to find a well suited architecture for a given application domain. We describe the architectural and generic principles of the KressArray family as well as the design flow for the determination of a domainspecific optimized KressArray architecture. Furthermore, we present the principles for the embedding of the KressArray into an accelerator engine, which can be used as a co-processor. Also, an overview about the tools in the CAD framework is given. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.computer.org/csdl/proceedings/fpga/2000/2592/00/25920222.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |