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Scalable Mismatch Correction for Time-interleaved Analog-to-Digital Converters in OFDM Reception
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sandeep, P. Madhow, U. |
| Copyright Year | 2009 |
| Abstract | Realization of all-digital baseband receiver processing for multi-Gigabit communication requires analog-to-digital converters (ADCs) of sufficient rate and output resolution.A promising architecture for this purpose is the time-interleaved ADC (TI-ADC), in which L “sub-ADCs” are employed in parallel. However, the gain, timing and voltage-offset mis matches between the sub-ADCs, if left uncompensated, lead to error fl oors in receiver performance. A standard technique for gain and timing mismatch correction is to use L FIR filters, with tap lengths increasing with the mismatch levels. In this paper,we investigate the use of TI-ADCs in OFDM receivers, and provide a scalable technique for mismatch compensation whose comple xity is independent ofL and the mismatch levels. We achieve this by decomposing the FFT operator that is at the core of the OFDM receiver into eigenmodes, and showing that, even for large v alues of L and mismatch levels as high as 25%, two eigenmodes suffice to provide an accurate description of the mismatch-perturbed FFT operator. We provide simulation results that show that the associated mismatch compensation algorithm is success ful is eliminating the mismatch-induced error floor. I. I NTRODUCTION The analog-to-digital converter (ADC) is a critical component in modern digital communication receivers, enablin g cost-effective, all-digital implementation of sophistic ated baseband signal processing algorithms. However, as communication bandwidths increase, the availability of ADCs with sufficient speed and resolution becomes a concern: Gigahert z bandwidths are required for emerging ultrawideband [1] and millimeter wave [2] applications, while 8-12 bits of resolu tion are required for providing enough dynamic range when operating in multipath environments with large constellations . The technology of choice at GHz speeds is “one shot” flash ADC, but it becomes unmanageable beyond 5 bits resolution, due to exponentially (in number of bits) increasing power consump tion and hardware complexity [3]. An attractive alternativ e [3] is a time-interleaved (TI) architecture, where high rate an d high resolution can be achieved by employing several low rate, high resolution, sub-ADCs in parallel. An ideal TI-AD C formed by time-interleaving four sub-ADCs is shown in Fig. 1 . However, an inherent problem with the TI-ADC architecture i s mismatch between the sub-ADCs, which to first order can be assumed to be gain, timing and voltage-offset mismatch [4]. Left uncompensated, such mismatch leads to error floors when TI-ADCs are employed in communication receivers. In this paper, we investigate scalable (as the number of sub-ADCs and the mismatch levels increase) mismatch compensation 1This research was supported in part by the National Science F oundation under grant CCF-0729222. techniques for removing mismatch-induced error floors due to TI-ADCs employed in OFDM reception. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://wcsl.ece.ucsb.edu/sites/wcsl.ece.ucsb.edu/files/publications/scalable_san.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
