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A post-processing system for an AHPL simulator
| Content Provider | Semantic Scholar |
|---|---|
| Author | Madhavan, Pundi Sreenivasan |
| Copyright Year | 1982 |
| Abstract | The main objective of this work, "A Post -processing System For An AHPL Simulator," is to enhance the use of the AHPL simulator in hardware design applications. The original AHPL simulator provides an output file which is difficult to analyze. The analysis of the output file is not convenient, particularly for larger number of variables and clock times. The original version of the simulator does not support features such as graphical presentation, display of a subset of the variables in given bounds of clock times and searching the output file for a given combination values of variables. All of the above -mentioned features are implemented in the post -processor. In the simulation of the AHPL sequence, from a design standpoint, the post -processor offers significant support. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://krex.k-state.edu/dspace/bitstream/handle/2097/36176/KSUL0022LD2668T41982M32.pdf?isAllowed=y&sequence=1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
