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Product term mode embedded memory arrays : algorithms and architectures
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2001 |
| Abstract | ..................................................................................................................................... .......ii List of Figures................................................................................................................................vii Acknowledgements.................................................................................................................... .....ix Chapter 1: Overview and Introduction ............................................................................... 1 1.1 Motivation...................................................................................................................... 1 1.2 Research Goals.............................................................................................................. 4 1.3 Research Approach ....................................................................................................... 6 1.4 Organization of This Thesis .......................................................................................... 7 Chapter 2: Background and Previous Work ...................................................................... 8 2.1 Programmable Logic: FPGAs and CPLDs.................................................................. 8 2.2 An Overview of FPGA Architectures.......................................................................... 10 2.2.1 Logic Resources ....................................................................................................... 10 Lookup-Tables......................................................................................................... 11 Product Terms.......................................................................................................... 14 2.2.2 Routing Resources............................................................................................... 16 Routing Between Logic Blocks............................................................................... 17 |
| File Format | PDF HTM / HTML |
| DOI | 10.14288/1.0065543 |
| Alternate Webpage(s) | http://www.ece.ubc.ca/~stevew/papers/pdf/lin_thesis.pdf |
| Alternate Webpage(s) | https://doi.org/10.14288/1.0065543 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
