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Design & Simulation Parallel Pipelined Radix-2 ^ 2 Fft Architecture for Real Valued Signals
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kapale, Madhavi S. Bodne, Nilesh P. |
| Copyright Year | 2015 |
| Abstract | The efficient implementation of FFT/IFFT processor for OFDM applications is presented. Indeed, the proposed radix-2^k feed-forward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. Multiplier make a parallel connection will give output in one clock cycle ,independent of the number cases form bit multiplier it requires n clock cycle which makes it slow so, for 16 clock cycle while in our case output will come in one clock cycle, when several samples in parallel must be processed. Multiplier make a parallel connection will give output in one clock cycle ,independent of the number cases form bit multiplier it requires n clock cycle which makes it slow so, for 16 clock cycle while in our case output will come in one clock cycle. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijesat.org/Volumes/2015_Vol_05_Iss_04/IJESAT_2015_05_04_05.pdf |
| Alternate Webpage(s) | http://ijesat.org/Volumes/2015_Vol_05_Iss_01/IJESAT_2015_05_01_08.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
