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Design of High Speed and Low Power Voltage Level Shifter in Dual Supply Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Ramya Priya, Vishnu |
| Copyright Year | 2018 |
| Abstract | This paper presents an efficient and low-power voltage level shifter for enhanced performance in dual-supply applications. The proposed circuit's efficiency is based on the fact that the strength of the pull-up device is lowered while the pull-down device pulls the output down. At the same time, the pull-down device's strength is increased by an auxiliary circuit that consumes low power. The proposed circuit is simulated in 0.18μm technology Cadence Virtuoso software. The simulation results show that the proposed circuit can convert extremely low level of input voltage into high output voltage level. That is, it can convert low input voltage VDDL=0.8V to high output voltage VDDH=3V with power dissipation of 8.7μW. Keywords—Voltage Level shifter, low power, Efficiency, power dissipation, voltage range. I.INTRODUCTION Static power dissipation and dynamic power dissipation are some sources of power consumption. In digital circuits, we can reduce this static power and dynamic power dissipation by reducing the power supply voltage. But the propagation delay of circuits increases while lowering the power supply voltage. In moderatespeed digital circuits or mixed-signal circuits, some parts operate at high speed; while some parts operate at low speed. In such circuits, instead of reducing the power supply voltage, we can use dual-supply architectures in which two supply voltages are used: low supply voltage (VDDL) and high supply voltage (VDDH). VDDL is supplied for blocks that operate at low speed, i.e., that are in non-crictical paths and (VDDH) is applied for those digital blocks that operate at high speed, i.e., in critical paths. In such a digital system with dualsupply architectures, voltage level shifter circuits are necessary so that they can convert the lower voltage levels into higher voltage levels to provide the needed voltage levels for the next blocks. To enhance the performance of the dual-supply systems, and to avoid the degradation of their performance, the voltage level shifters used should be designed with reduced propagation delay, low power consumption and reduced silicon area. And also to save more power, the voltage level shifters should be capable of converting very low VDDL values to values below the input transistors' threshold voltage. Therefore, in this paper, an efficient and low power voltage level shifter is proposed. This proposed shifter can convert even very low input voltages into high voltages at the output. The remaining of this paper is structured as follows. Analysis of some conventional voltage level shifters in given in Section I |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://trendytechjournals.com/au2.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
