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A Semi-Digital Delay Locked Loop with Unlimited Phase Shift Capability and 0 . 08-400 MHz
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sidiropoulos, Stefanos Horowitz, Mark |
| Copyright Year | 1997 |
| Abstract | Delay locked loops are an attractive alternative to VCO based phase locked loops due to their simpler design and inherent stability [1]-[3]. The primary disadvantage of conventional DLLs is their limited phase range, which limits their application to mesochronous environments. This dual DLL architecture combines several techniques to achieve unlimited phase shift, low jitter and large operating range. The desired delay is generated by phase interpolation [2], but the use of tighter spaced 30° edges results in lower noise sensitivity. Owing to its digital control [4] but avoiding the use of a VCO, the DLL can operate with just periodic calibration. Finally, by utilizing self-biasing [3] it achieves large operating range and low jitter. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://velox.stanford.edu/~sidirop/papers/isscc97.ps |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
