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An Efficient VLSI Architecture for CORDIC Algorithm
| Content Provider | Semantic Scholar |
|---|---|
| Author | Parameshwaran, R. Hariharan, K. Manikandan, R. Raguram, M. Narendran, B. |
| Copyright Year | 2013 |
| Abstract | The proposed architecture carried out makes use of n iterations to produce the final value of the function upto an accuracy of n bits. A two's complement 4bit carry-look ahead adder/subtractor block with carry-save has been implemented as part of the architecture for greater speed. An 8-bit barrel shifter has been implemented for use in the algorithm. An optimum use of edge-triggered latches and an intelligent clocking scheme has been designed to reduce the number of transistors involved. The iterative sequencing of steps requires a 3-bit counter and a clocking control scheme which has been implemented in this project. The CORDIC algorithm requires a certain set of fixed values to be accessed during the implementation of the iterative series of steps. A read-only-memory (ROM) block has been designed for this purpose and can be accessed through a 3-bit address bus whose bits are set by the outputs of the 3-bit counter. Keywords—CORDIC, Booth recoding, Online CORDIC, vector translation, coarse rotation. Introduction CORDIC algorithm has found its way in many applications. The CORDIC was introduced in 1956 by Jack Volder as a highly efficient, low-complexity, and robust technique to compute the elementary functions. It is initially intended for navigation technology, the CORDIC algorithm has found its way in a wide range of applications, 1898 R.Parameshwaran et al ranging from pocket calculators, numerical co-processors, to high performance radar signal processing. After invention CORDIC worked as the replacement for the analog navigation computers aboard the B-58 supersonic bomber aircraft with a digital counterpart. Pirsch.P(1998) The CORDIC airborne navigational computer built for this purpose, outperformed conventional contemporary computers by a factor of 7, mainly due to the revolutionary development of the CORDIC algorithm. Further Steve Walther continues work on CORDIC, with the application of the CORDIC algorithm in the Hewlett-Packard calculators, such as the HP-9100 and the famous HP-35 in year 1972, the HP-41C in year1980. He told how the unified CORDIC algorithm i.e. combining rotations in the circular, hyperbolic, and linear coordinate systems and how it was applied in the HP-2116 floating-point numerical co-processor. Today fast rotation techniques are closely related to CORDIC, to perform orthonormal rotation at a very low cost. Although fast rotations exist for certain angles only, they are sufficiently versatile, and have already been widely applied in signal processing. Andraka. R. ( 1998) The basic block diagram of CORDIC processor is shown in Fig 2.1. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.researchgate.net/profile/R_Manikandan/publication/259497554_An_Efficient_VLSI_Architecture_for_CORDIC_Algorithm/links/0046352de0a6acacd4000000.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
