Caracterització a escala nanomètrica de la degradació I. Ruptura dielèctrica del SiO2 en dispositius MOS mitjançant CAFM

Content Provider	Semantic Scholar
Author	Pujal, M.
Copyright Year	2003
Abstract	La progressiva reduccio del gruix de loxid de porta (SiO2) en dispositius MOS sense el corresponent escalat en tensions, ha donat lloc a laparicio de mecanismes de fallada (ruptura forta, HBD; ruptura suau, SBD; ruptura progressiva, PBD; o corrents de fuites, SILC) que en limiten la seva fiabilitat. Alguns daquests mecanismes, menys severs que la ruptura forta (SBD, PBD i SILC), han plantejat nous interrogants a lhora destablir la relacio que hi ha entre la ruptura (BD) de loxid i la fallada del dispositiu o circuit del qual forma part. Per aquest motiu, a fi de determinar el grau de sensibilitat dels circuits a la ruptura dielectrica, cal estudiar amb mes profunditat els factors que en controlen la seva severitat. En aquest sentit, els tests estandards de caracteritzacio electrica no representen de manera gaire acurada les condicions reals destres dels dispositius MOS. Treballs recents, en canvi, indiquen que lestres limitat en corrent (CLS), si permet simular millor les condicions reals doperacio. Actualment es ampliament acceptat que la ruptura de loxid es (i) un fenomen extremadament local que es desencadena en arees de lordre de 10-13-10-12cm2 i (ii) la consequencia dun proces de degradacio en el qual lestructura de loxid es modifica progressivament i que sha associat a la generacio de trampes durant lestres electric. El caracter extremadament local daquests fenomens fa que sigui necessaria una analisi a la mateixa escala on tenen lloc: a escala nanometrica. Amb aquesta finalitat, en aquesta tesi sha analitzat la fenomenologia de pre- i post-ruptura en capes primes de SiO2 (2.9-5.9nm) amb C-AFM (Conductive Atomic Force Microscope). Lelevada resolucio lateral daquesta tecnica (~10nm) ha permes caracteritzar la degradacio i la ruptura dielectrica (aixi com lefecte del limit de corrent) doxids de porta a escala nanometrica. Durant letapa de degradacio, shan observat canvis sobtats i transitoris en la conductivitat de loxid, atribuits a latrapament/ desatrapament de carregues elementals en els defectes generats durant lestres electric. Aquesta fenomenologia sha relacionat amb el soroll de pre-ruptura observat en dispositius de grandaria microelectronica. El soroll de pre-ruptura sha registrat en estressos a tensio constant (CVS) en forma de RTS (Random Telegraph Signal). Una analisi temporal i frequencial demostra que els resultats obtinguts son compatibles amb els corresponents a estructures amb electrode de porta. A mes, amb C-AFM sha pogut mesurar duna manera directa la caracteristica I-V dun spot de pre-ruptura i sha trobat que te un comportament similar a lobservat en memories flash amb corrents de fuites anomals. En aquesta tesi tambe sha analitzat la ruptura de loxid, fent especial emfasi en els efectes del limit de corrent en lesdeveniment BD. Oxids de porta sense electrode metal.lic shan estressat amb la punta del microscopi amb i sense limit de corrent fins a desencadenar la ruptura. Despres de lesdeveniment BD, shan registrat corrents mes elevats en la zona afectada i, en alguns casos, tambe shan observat canvis en les imatges topografiques. Aquests canvis morfologics shan relacionat amb la carrega electrica negativa present a loxid despres de la ruptura (BINC), que sha associat amb el mal estructural induit durant lesdeveniment BD. La quantitat de BINC sha estimat a partir de les alcades de les protuberancies observades en les imatges topografiques obtingudes amb C-AFM i sha trobat que es superior en el cas destressos sense limit de corrent. A partir de les imatges de corrent tambe sha trobat que la ruptura, tot i desencadenar-se en arees molt petites (de lordre de ~100nm2), es propaga lateralment a arees veines SBD. El valor de SBD es veu fortament afectat per la severitat de la ruptura dielectrica que, al mateix temps, depen del corrent que flueix a traves de loxid en el moment en el qual es desencadena lesdeveniment BD. Quan sapliquen CLS, SBD esta limitada a un area de ~3.1 104nm2 mentre que, quan no hi ha limit de corrent, les arees afectades son superiors (~1.6 105nm2). Aquests resultats doncs, demostren que el limit de corrent no permet el desenvolupament complet del canal percolatiu, deixant loxid en un estat metaestable que es perllonga fins que les condicions electriques destres canvien. Finalment, tambe sha demostrat que amb C-AFM es possible localitzar i analitzar spots de ruptura induits en dispositius microelectronics (amb electrode de porta) mitjancant les tecniques de caracteritzacio estandard. Tots aquests resultats demostren la capacitat del C-AFM danalitzar en detall lefecte del limit de corrent en la ruptura dielectrica, aixi com limpacte de la ruptura en la funcionalitat del dispositiu microelectronic. The progressive decrease of the gate oxide (SiO2) thickness in MOS devices without the corresponding bias voltages scaling, has provoked the appearance of failure mechanisms (hard breakdown, HBD; soft breakdown, SBD; progressive breakdown, PBD; and the stress induced leakage current, SILC) that limit the oxide reliability. Some of these mechanisms (SBD, PBD and SILC) are not as hard as the HBD event, and that has questioned the relation between the oxide breakdown (BD) and the device or circuit failure. For this reason, to determine the actual sensitivity of circuits to oxide breakdown, it is necessary to study the factors that control the severity of the BD event. In this direction, the standard electrical tests are not representative of the actual stress conditions of MOS devices. Recent works, however, point out the current limited stress (CLS) as a better testing methodology to simulate the actual operation conditions. Nowadays it is accepted that the oxide failure is (i) an extremely local phenomenon that takes place in areas of the order of 10-12-10-13cm2 and (ii) the consequence of a degradation stage during which the oxide structure is progressively modified, and that has been associated to the generation of defects during the electrical stress. The extremely local nature of both phenomenon makes necessary an analysis at the same scale where they take place: at a nanometer scale. With this purpose, in this thesis the pre- and post-BD phenomenology has been analysed in thin SiO2 films (2.9-5.9nm) with C-AFM (Conductive Atomic Force Microscope). The high lateral resolution of this technique (~10nm) allows the electrical characterization of the degradation and breakdown event (as well as the effect of the current limitation) of gate oxides at a nanometer scale. During the degradation stage, sudden changes of the oxide conductivity have been observed, attributed to the trapping/detrapping of elementary charges in/from the defects generated during the electrical stress. This phenomenology has been related to the pre-BD noise observed in microelectronic devices. This pre-BD noise is measured during a Constant Voltage Stress (CVS) in form of Random Telegraph Signal (RTS). A time and frequency analysis show compatible parameters to those obtained in poly-gated structure. Moreover, the C-AFM has allowed the direct measurement of the I-V curve of a fluctuating spot, which has been found to be similar to those reported for the anomalous leakage current in flash memory devices. The BD of the oxide has been also analysed in this thesis, paying an special attention to the effects of a current limitation during the BD transient. Bare oxides have been stressed until BD using the tip of the microscope as the metal electrode, with and without setting a current limit. After BD, larger currents are measured at the BD location (as expected) and, sometimes, some changes are also observed in the topography images. These morphological changes have been related to the negative charge present in the oxide after the oxide BD (BINC), which has been associated to the structural damage induced by the BD event. The amount of BINC has been quantified from the heights of the hillocks observed in the C-AFM topography images and has been found to be larger in the case of non-limited current stresses. From the current images, it has been shown that, although the BD takes place in a very small area (So, few hundreds of nm2) it is laterally propagated to a larger area, SBD. The value of SBD is strongly affected by the BD hardness which, at the same time, depends on the current that flows at the location where BD is triggered. When CLS are applied, the growth of SBD is limited to an area of ~3.1 104nm2 whereas, when there is no current limit, larger areas are affected ( ~1.6 105nm2). The results also show that the current limit does not allow the complete development of the BD path, leaving the oxide in a metastable configuration that lasts until the electrical environment is changed. Finally, it has also been demonstrated that with C-AFM it is possible to locate and characterize BD spots induced in microelectronic devices (poly-gated) with standard electrical tests. The results show that C-AFM is a powerful tool to analyze in detail the effect of current limitation on the breakdown event and, conversely, the impact of BD on the device and circuit performance.
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