Implementation and Optimization of Asymmetric Transistors in Advanced SOI CMOS Technologies for High Performance

Content Provider	Semantic Scholar
Author	Hoentschel, Jan Wei, Aijia Wiatr, Maciej Gehring, Andreas Scheiper, Thilo Mulfinger, Robert Feudel, Th. Lingner, Th. Poock, Andre Mühle, Silvia Krüger, Carmen Herrmann, Torsten Klix, Wilfried Stenzel, Roland Stephan, Rolf Huebler, Peter Kammler, Thorsten Raab, Michael Greenlaw, David Horstmann, Marcel
Copyright Year	2008
Abstract	Sub-40nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12 % and 10 %, respectively, resulting in performance at 1.0 V and 100 nA/μm IOFF of NIDSAT = 1354 μA/μm and PIDSAT = 857 μA/μm. Product-level implementation of asymmetric transistors showed a speed benefit of 12 %, at matched yield and improved reliability.
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Alternate Webpage(s)	https://www.htw-dresden.de/fileadmin/userfiles/et/Personal/Professoren/Stenzel/Veroeffentlichungen/iedm2008.pdf
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article