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A universal self-calibrating Dynamic Voltage and Frequency Scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs
| Content Provider | Semantic Scholar |
|---|---|
| Author | Zhao, Shuze Ahmed, Ibrahim Lamoureux, Carl Lotfi, Ashraf W. Betz, Vaughn Trescases, Olivier |
| Copyright Year | 2016 |
| Abstract | Field Programmable Gate Arrays (FPGAs) are widely used in telecom, medical, military and cloud computing applications. Unlike in microprocessors, the routing and critical path delay of FPGAs is user dependent. The design tool suggests a maximum operating frequency based on the worst-case timing analysis of the critical paths at a fixed nominal voltage, which usually means there is significant voltage or frequency margin in a typical chip. This paper presents a universal offline self-calibration scheme, which automatically finds the FPGA frequency and core voltage operating limit at different self-imposed temperatures by monitoring design-specific critical paths. These operating points are stored in a calibration table and used to dynamically adjust the frequency and core voltage according to the FPGA temperature when the application circuit is running. The self-calibration process is demonstrated on an Altera Cyclone IV 65-nm FPGA with a digitally controlled dc-dc converter, leading to 40% power savings in a typical digital filter application. |
| Starting Page | 1882 |
| Ending Page | 1887 |
| Page Count | 6 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/APEC.2016.7468125 |
| Alternate Webpage(s) | http://www.ele.utoronto.ca/~ot/publications/papers/c50_zhao_apec2016.pdf |
| Alternate Webpage(s) | http://www.eecg.utoronto.ca/~vaughn/papers/apec2016_dvs.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/APEC.2016.7468125 |
| Journal | 2016 IEEE Applied Power Electronics Conference and Exposition (APEC) |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
