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Improved clock-gating through transparent pipelining
| Content Provider | Semantic Scholar |
|---|---|
| Author | Jacobson, H. M. |
| Copyright Year | 2004 |
| Abstract | This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accumulate unit design. Transistor level simulations show that dynamic clock power dissipation can be reduced by 40-60% at pipeline utilization factors between 20-60%, on top of traditional stage-level clock gating, without affecting pipeline latency or throughput. |
| Starting Page | 26 |
| Ending Page | 31 |
| Page Count | 6 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.computer.org/csdl/proceedings/islped/2004/2626/00/01349302.pdf |
| Journal | Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
