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Design of Run-time signal test architecture in IEEE 1149.1
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kim, Jeong-Hong Kim, Young-Sig Kim, Jae-Soo |
| Copyright Year | 2010 |
| Abstract | IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate. |
| Starting Page | 13 |
| Ending Page | 21 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.9708/jksci.2010.15.1.013 |
| Volume Number | 15 |
| Alternate Webpage(s) | http://ocean.kisti.re.kr/downfile/volume/tkioa/CPTSCQ/2010/v15n1/CPTSCQ_2010_v15n1_13.pdf |
| Alternate Webpage(s) | https://doi.org/10.9708/jksci.2010.15.1.013 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
