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Pipelining of digit-serial processing elements in recursive digital filters
| Content Provider | Semantic Scholar |
|---|---|
| Author | Karlsson, Malin Vesterbacka, Mark Kulesza, Wlodek |
| Copyright Year | 2004 |
| Abstract | In this paper, performance trade-offs between throughput, and energy consumption, in implementation of recursive digital filters are presented. Digit-serial arithmetic with different degree of pipelining are used in the implementions. As a demonstration object, a bireciprocal thirdorder lattice wave digital filter is used. Simulations with HSPICE show that a maximum throughput is obtained using pipelined processing elements with a digit-size equal to the fractional bits in the filter coefficient. The use of nonpipelined processing elements yields minimum energy consumption. A trade-off between throughput and energy consumption can be made by pipelining only some of the processing elements. |
| Starting Page | 129 |
| Ending Page | 132 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://wooster.hut.fi/publications/norsig2004/40_KARLS.PDF |
| Alternate Webpage(s) | http://legacy.spa.aalto.fi/sig-legacy/norsig2004/publications/40_KARLS.PDF |
| Journal | Proceedings of the 6th Nordic Signal Processing Symposium, 2004. NORSIG 2004. |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |