NDLI: Recon fi gurable Computing Systems for Digital RF Closed-Loop Controls ∗

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Recon fi gurable Computing Systems for Digital RF Closed-Loop Controls ∗

Content Provider	Semantic Scholar
Author	Zipf, Peter Guntoro, Andre Glesner, Manfred Klingbeil, Harald
Copyright Year	2007
Abstract	For the development of the SIS100/300 accelerator, the required beam stability and manipulation tasks can only be accomplished by specific control mechanisms. Digital algorithms enable a much higher precision and flexibility for processing, filtering, open and closed-loop control of signals than analogue techniques. Their main workload is characterised by the processing of continuous data streams. The software-driven processing of data streams using digital signal processor (DSP) systems, as currently used by the GSI for building the cavity synchronisation system, poses a capacity limit due to the block-wise computations and limited I/O bandwidth of the processors. The availability of reconfigurable hardware (field-programmable gate arrays, FPGA) opens new opportunities for the provision of computing power: Hardware functionality can be ”programmed” into an FPGA on demand, a technique known as structural programming. Like this, stream-based algorithms, e.g., a FIR filter, can be directly implemented in fast hardware structures. Instead of loading and executing instructions working on stored data, the streams can directly be fed into the functional unit, e.g., working as a pipeline. The primary objective of our work is the development of optimised hardware architectures for this kind of system, based on the migration of initial software solutions into faster FPGA hardware.
File Format	PDF HTM / HTML
Alternate Webpage(s)	http://www.gsi.de/informationen/wti/library/scientificreport2006/PAPERS/FAIR-ACCELERATORS-21.pdf
Alternate Webpage(s)	http://www.gsi.de/scirep2006/PAPERS/FAIR-ACCELERATORS-21.pdf
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

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