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Block-level Prediction for Wide-issue Superscalar Processors
| Content Provider | Semantic Scholar |
|---|---|
| Author | Dutta, Simonjit Franklin, Manoj |
| Copyright Year | 1995 |
| Abstract | Changes in control ow, caused primarily by conditional branches, are a prime impediment to the performance of wide-issue superscalar processors. This paper investigates a block-level prediction scheme to mitigate the eects of control ow changes caused by conditional branches. Instead of predicting the outcome of each conditional branch individually, this scheme predicts the target of a sequential block of instructions, thereby allowing the superscalar processor to go past multiple branches per cycle. This approach is evaluated using the MIPS architecture, for 8-way and 12-way superscalar processors, and an improvement in eective fetch size of approximately 15% and 25%, respectively, over identical processors that use branch prediction is observed. No appreciable dierence in the prediction accuracy was observed, although block-level prediction predicted one out of four outcomes. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ces.clemson.edu/~ilp/icapp.ps |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Branch (computer science) Branch predictor Central processing unit Superscalar processor Symmetric multiprocessing Wide-issue |
| Content Type | Text |
| Resource Type | Article |
